PM=DEFAULT, SLEEPFLAG=ACTIVE_MODE, DPDFLAG=NOT_DEEP_POWER_DOWN
Power control register
| PM | Power mode 0 (DEFAULT): Default. The part is in active or sleep mode. 1 (DEEP_SLEEP): Deep-sleep. ARM WFI will enter Deep-sleep mode. 2 (POWER_DOWN): Power-down. ARM WFI will enter Power-down mode. 3 (DEEP_POWER_DOWN): Deep power-down. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down). |
| NODPD | A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. |
| RESERVED | Reserved. Do not write ones to this bit. |
| SLEEPFLAG | Sleep mode flag 0 (ACTIVE_MODE): Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect. 1 (LOW_POWER_MODE): Low power mode. Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. |
| RESERVED | Reserved. Do not write ones to this bit. |
| DPDFLAG | Deep power-down flag 0 (NOT_DEEP_POWER_DOWN): Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect. 1 (DEEP_POWER_DOWN): Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. |
| RESERVED | Reserved. Do not write ones to this bit. |